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CS51021A, CS51022A, CS51023A, CS51024A Enhanced Current Mode PWM Controller
The CS51021A/2A/3A/4A Fixed Frequency PWM Current Mode Controller family provides all necessary features required for AC-DC or DC-DC primary side control. Several features are included eliminating the additional components needed to implement them externally. In addition to low startup current (75 mA) and high frequency operation capability, the CS51021A/2A/3A/4A family includes overvoltage and undervoltage monitoring, externally programmable dual threshold overcurrent protection, current sense leading edge blanking, current slope compensation, accurate duty cycle control and an externally available 5.0 V reference. The CS51021A and CS51023A feature bidirectional synchronization capability, while the CS51022A and CS51024A offer a sleep mode with 100 mA maximum IC current consumption. The CS51021A/2A/3A/4A family is available in a 16 lead narrow body SOIC package.
Device CS51021A CS51022A CS51023A CS51024A Sleep/Synch Synch Sleep Synch Sleep VCC Start/Stop 8.25 V/7.7 V 8.25 V/7.7 V 13 V/7.7 V 13 V/7.7 V GATE ISENSE SLEEP or SYNC SLOPE UV OV RTCT ISET CS5102xAG AWLYWW
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16 1
SOIC-16 D SUFFIX CASE 751B
16 1
TSSOP-16 DTB SUFFIX CASE 948F
PIN CONNECTIONS AND MARKING DIAGRAMS
1 16 VC PGND VCC VREF LGND SS COMP VFB
Features * 75 mA Max. Startup Current * Fixed Frequency Current Mode Control * 1.0 MHz Switching Frequency * Undervoltage Protection Monitor * Overvoltage Protection Monitor with Programmable Hysteresis * Programmable Dual Threshold Overcurrent Protection with Delayed Restart * Programmable Soft Start * Accurate Maximum Duty Cycle Limit * Programmable Slope Compensation * Leading Edge Current Sense Blanking * 1.0 A Sink/Source Gate Drive * Bidirectional Synchronization (CS51021A/3A) * 50 ns PWM Propagation Delay * 100 mA Max Sleep Current (CS51022A/4A) * Pb-Free Packages are Available*
1 CS51 022A ALYW G G x A WL, L Y WW, W G or G
16
= Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
February, 2006 - Rev. 8
Publication Order Number: CS51021A/D
CS51021A, CS51022A, CS51023A, CS51024A
100 VIN (36 V to 72 V) PGND 51 k BAS21 18 V 100:1 FZT688
10
1.0 mF
SYNC/SLEEP
22 mF
11 V 200 k, 1.0% 2.49 k, 1.0% BA521
2:5
10 k
24.3 k, 1.0%
4:1
VOUT (5 V/5 A)
0.01 mF 10 k
4700 pF 22 k 51 k
330 pF
VC VREF COMP VFB RTCT SYNC/ SLEEP CSS LGND
VCC UV OV ISET SLOPE GATE ISENSE PGND
470 pF
10
100 mF 100 mF SGND
CS51021A/2A
680 pF
IRF6345 6.98 k, 1.0% 6.98 k, 1.0%
100 62 100 p
0.01 mF
0.1 mF TL431 180 1.0 k 10 K 1.0 K MOC81025
5.1 k
1000 pF 2.0 k, 1.0%
2.0 k, 1.0%
Figure 1. Typical Application Diagram, 36-72 V to 5.0 V, 5.0 A DC-DC Converter
MAXIMUM RATINGS*
Rating Power Supply Voltage, VCC Driver Supply Voltage, VC SYNC, SLEEP, RTCT, SOFT-START, VFB, SLOPE, ISENSE, UV, OV, ISET (Logic Pins) Peak GATE Output Current Steady State Output Current Operating Junction Temperature, TJ Storage Temperature Range, TS ESD (Human Body Model) Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) Value -0.3, 20 -0.3, 20 0.25 to VREF 1.0 0.2 150 -65 to +150 2.0 230 peak Unit V V V A A C C kV C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. *The maximum package power dissipation must be observed. 1. 60 second maximum above 183C.
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CS51021A, CS51022A, CS51023A, CS51024A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for -40C < TA < 85C, -40C < TJ < 150C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kW, CT = 390 pF)
Characteristic Under Voltage Lockout START Threshold (CS51021A/2A) START Threshold (CS51023A/4A) STOP Threshold Hysteresis (CS51021A/2A) Hysteresis (CS51023A/4A) ICC @ Startup (CS51021A/2A) ICC @ Startup (CS51023A/4A) ICC Operating (CS51021A/3A) ICC Operating (CS51022A/4A) ICC Operating Voltage Reference Initial Accuracy Total Accuracy Line Regulation Load Regulation NOISE Voltage OP Life Shift FAULT Voltage OK Voltage OK Hysteresis Current Limit Error Amplifier Initial Accuracy Reference Voltage VFB Leakage Current Open Loop Gain Unity Gain Bandwidth COMP Sink Current COMP Source Current COMP High Voltage COMP Low Voltage PS Ripple Rejection SS Clamp, VCOMP ILIM(SET) Clamp TA = 25C, IREF = 2.0 mA, VCC = 14 V, VFB = COMP, (Note 2) VFB = COMP VFB = 0 V 1.4 V < COMP < 4.0 V, (Note 2) (Note 2) COMP = 1.5 V, VFB = 2.7 V COMP = 1.5 V, VFB = 2.3 V VFB = 2.3 V VFB = 2.7 V FREQ = 120 Hz, (Note 2) VSS = 2.5 V, VFB = 0 V, ISET = 2.0 V (Note 2) 2.465 2.440 - 60 1.5 2.0 -0.2 4.35 0.4 60 2.4 0.95 2.515 2.515 -0.2 90 2.5 6.0 -0.5 4.8 0.8 85 2.5 1.0 2.565 2.590 -2.0 - - - - 5.0 1.2 - 2.6 1.15 V V mA dB MHz mA mA V V dB V V TA = 25C, IREF = 2.0 mA, VCC = 14 V, (Note 2) 1.0 mA < IREF < 10 mA 8.2 V < VCC < 18 V, IREF = 2.0 mA 1.0 mA < IREF < 10 mA (Note 2) T = 1000 Hours, (Note 2) Force VREF Force VREF Force VREF Force VREF 4.95 4.9 - - - - 0.90 x VREF 0.94 x VREF 75 -20 5.0 5.0 6.0 6.0 50 4.0 0.93 x VREF 0.96 x VREF 165 - 5.05 5.15 20 15 - 20 0.95 x VREF 0.985 x VREF 250 - V V mV mV mV mV V V mV mA Includes 1.0 nF Load - - - - - VCC < UVSTART Threshold VCC < UVSTART Threshold - - 7.95 12.4 7.4 0.50 4.0 - - - - - 8.25 13 7.7 0.75 5.0 40 45 7.0 6.0 7.0 8.8 13.4 8.2 1.00 6.0 75 75 9.0 8.0 12 V V V V V mA mA mA mA mA Test Conditions Min Typ Max Unit
2. Guaranteed by design, not 100% tested in production.
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3
CS51021A, CS51022A, CS51023A, CS51024A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for -40C < TA < 85C, -40C < TJ < 150C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kW, CT = 390 pF)
Characteristic Oscillator Accuracy Voltage Stability Temperature Stability Min Charge & Discharge Time Duty Cycle Accuracy Peak Voltage Valley Voltage Valley Clamp Voltage Discharge Current Discharge Current Synchronization (CS51021A/3A) Input Threshold Output Pulsewidth Output High Voltage Input Resistance Drive Delay Output Drive Current SLEEP (CS51022A/4A) SLEEP Input Threshold SLEEP Input Current ICC @ SLEEP GATE Driver HIGH Voltage LOW Voltage HIGH Voltage Clamp LOW Voltage Clamp Peak Current UVL Leakage RISE Time FALL Time SLOPE Compensation Charge Current COMP Gain Discharge Voltage SLOPE = 2.0 V Fraction of slope voltage added to ISENSE, (Note 3) SYNC = 0 V -63 0.095 - -53 0.100 0.1 -43 0.105 0.2 mA V/V V Measure VC - GATE, VC = 10 V, 150 mA Load Measure GATE - PGND, 150 mA SINK VC = 20 V, 1.0 nF Measured at 10 mA Output Current VC = 20 V, 1.0 nF, (Note 3) VC = 20 V measured at 0 V Load = 1.0 nF, 1.0 V < GATE < 9.0 V, VC = 20 V, TA = 25C Load = 1.0 nF, 9.0 V > GATE > 1 .0 V, VC = 20 V - - 11 - - - - - 1.5 1.2 13.5 0.6 1.0 -1.0 60 15 2.2 1.5 16 0.8 - -50 100 40 V V V V A mA ns ns Active High VSLEEP = 4.0 V VCC 15 V 1.0 11 - 1.5 25 50 2.7 46 100 V mA mA ISYNC = 100 mA (Note 3) SYNC to GATE RESET 1.0 k Load - - 1.0 160 3.5 35 80 1.25 1.5 260 4.3 70 120 2.0 2.7 400 4.8 140 150 3.5 V ns V kW ns mA TA = 25C, Note 3 RT = 12 k, CT = 390 pF Delta Frequency 8.2 V < VCC < 20 V TMIN < TA < TMAX, (Note 3) (Note 3) RT = 12 k, CT = 390 pF (Note 3) (Note 3) 10 k Resistor to ground on RTCT - 230 - - 0.333 70 - - 1.2 0.8 0.925 255 2.0 8.0 - 77 3.0 1.5 1.4 1.0 1.0 280 3.0 - - 83 - - 1.6 1.2 1.075 kHz % % ms % V V V mA mA Test Conditions Min Typ Max Unit
3. Guaranteed by design, not 100% tested in production.
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CS51021A, CS51022A, CS51023A, CS51024A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for -40C < TA < 85C, -40C < TJ < 150C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kW, CT = 390 pF)
Characteristic Current Sense OFFSET Voltage Blanking Time Blanking Disable Voltage Second Current Threshold Gain ISENSE Input Resistance Minimum On Time Gain OV & UV Voltage Monitors OV Monitor Threshold OV Hysteresis Current UV Monitor Threshold UV Monitor Hysteresis SOFT START (SS) Charge Current Discharge Current Charge Voltage, VSS Discharge Voltage, VSS 4. Guaranteed by design, not 100% tested in production. SS = 2.0 V SS = 2.0 V - - -70 250 4.4 0.25 -55 1000 4.7 0.27 -40 - 5.0 0.30 mA mA V V - - - - 2.4 -10 1.38 25 2.5 -12.5 1.45 75 2.6 -15 1.52 100 V mA V mV GATE High to Low (Note 4) Adjust VFB - - (Note 4) - 0.09 - 1.8 1.21 - 30 0.78 0.10 55 2.0 1.33 5.0 70 0.80 0.11 160 2.2 1.45 - 110 0.82 V ns V V/V kW ns V/V Test Conditions Min Typ Max Unit
PACKAGE PIN DESCRIPTION
PIN # PIN SYMBOL FUNCTION
16 Lead SO Narrow 1 2 3 3 4 5 6 7 8 9 10 GATE ISENSE SYNC (CS51021A/3A) SLEEP (CS51022A/4A) SLOPE UV OV RTCT ISET VFB COMP External power switch driver with 1.0 A peak capability. Current sense amplifier input. Bi-directional synchronization. Locks to the highest frequency. Active high chip disable. In sleep mode, VREF and GATE are turned off. Additional slope to the current sense signal. Internal current source charges the external capacitor. Undervoltage protection monitor. Overvoltage protection monitor. Timing resistor RT and capacitor CT determine oscillator frequency and maximum duty cycle, DMAX. Voltage at this pin sets pulse-by-pulse overcurrent threshold, and second threshold (1.33 times higher) with Soft Start retrigger (hiccup mode). Feedback voltage input. Connected to the error amplifier inverting input. Error amplifier output. Frequency compensation network is usually connected between COMP and VFB pins. Charging external capacitor restricts error amplifier output voltage during the start or fault conditions (hiccup). Logic ground. 5.0 V reference voltage output. Logic supply voltage. Output power stage ground connection. Output power stage supply voltage.
11 12 13 14 15 16
SS LGND VREF VCC PGND VC
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CS51021A, CS51022A, CS51023A, CS51024A
VCC
+
LGND
VCC_OK VREF = 5.0 V
VREF
-
+
Start Stop
-
VREF_OK
- +
4.75 V
+
VC
SLEEP SYNC RTCT 4.3 V
200 ns
-
OSC S Q G2 D4 ZD1
13.5 V
GATE
+
SS Clamp
F1
-
COMP
D2
-
ISET Clamp
G1
R PGND
+ + 2.5 V -
VFB VREF
53 mA
+
E/A
D3 20 k
-
PWM Comp
VREF
55 mA
- -
VFB Monitor
D1 10 k
+
-
SS Monitor
SS
+ -
2.0 V
+
G4 DISABLE
+
+ -
4.7 V
SLOPE ISENSE Q2
0.1 V 0.1 0.8
-
+
55 ns Blank VISENSE
+
2nd 1.33 VREF 12.5 mA
Threshold
G3 FAULT
ISET
- +
OV Monitor
Discharge Latch
OV
-
UV Monitor
UV
+ -
2.5 V
-
+
1.45 V
+ -
Figure 2. Block Diagram
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CS51021A, CS51022A, CS51023A, CS51024A
CIRCUIT DESCRIPTION
200 ns 4.3 V
Current Sense and Protection
SYNC
RTCT 0V
TCH VSLOPE TDIS
0V
SLOP E IS
0V
IS + 0.1 SLOPE
VCOMP
55 ns Blanking
IS
PWM COMP
0V
The current is monitored at the ISENSE pin. The CS51021A/2A/3A/4A has leading edge blanking circuitry that ignores the first 55 ns of each switching period. Blanking is disabled when VFB is less than 2.0 V so that the minimum on-time of the controller does not have an additional 55 ns of delay time during fault conditions. For the remaining portion of the switching period, the current sense signal, combined with a fraction of the slope compensation voltage, is applied to the positive input of the PWM comparator where it is compared with the divided by three error amplifier output voltage. The pulse-by-pulse overcurrent protection threshold is set by the voltage at the ISET pin. This voltage is passed through the ISET Clamp and appears at the non-inverting input of the PWM comparator, limiting its dynamic range according to the following formula:
Overcurrent Threshold + 0.8 VI(SENSE) ) 0.1 V ) 0.1 VSLOPE
GATE 0V
where
VI(SENSE) is voltage at the ISENSE pin.
VDS
VIN 0V
and
VSLOPE is voltage at the SLOPE pin.
Figure 3. Typical Waveforms
THEORY OF OPERATION
Powering the IC
The IC has two supply and two ground pins. VC and PGND pins provide high speed power drive for the external power switch. VCC and LGND pins power the control portion of the IC. The internal logic monitors the supply voltage, VCC. During abnormal operating conditions, the output is held low. The CS51021A/2A/3A/4A requires only 75 mA of startup current.
Voltage Feedback
During extreme overcurrent or short circuit conditions, the slope of the current sense signal will become much steeper than during normal operation. Due to loop propagation delay, the sensed signal will overshoot the pulse-by-pulse threshold eventually reaching the second overcurrent protection threshold which is 1.33 times higher than the first threshold and is described by the following equation:
2nd Threshold + 1.33 VI(SET)
Exceeding the second threshold will reset the Soft Start capacitor CSS and reinitiate the Soft Start sequence, repeating for as long as the fault condition persists.
Soft Start
The output voltage is monitored via the VFB pin and is compared with the internal 2.5 V reference. The error amplifier output minus one diode drop is divided by 3 and connected to the negative input of the PWM comparator. The positive input of the PWM comparator is connected to the modified current sense signal. The oscillator turns the external power switch on at the beginning of each cycle. When current sense ramp voltage exceeds the reference side of PWM comparator, the output stage latches off. It is turned on again at the beginning of the next oscillator cycle.
During power up, when the output filter capacitor is discharged and the output voltage is low, the voltage across the Soft Start capacitor (VSS) controls the duty cycle. An internal current source of 55 mA charges CSS. The maximum error amplifier output voltage is clamped by the SS Clamp. When the Soft Start capacitor voltage exceeds the error amplifier output voltage, the feedback loop takes over the duty cycle control. The Soft Start time can be estimated with the following formula:
tSS + 9 10 4 CSS
The Soft Start voltage, VSS, charges and discharges between 0.25 V and 4.7 V.
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CS51021A, CS51022A, CS51023A, CS51024A
Slope Compensation
DC-DC converters with current mode control require a current sense signal with slope compensation to avoid instability at duty cycles greater than 50%. Slope capacitor CS is charged by an internal 53 mA current source and is discharged during the oscillator discharge time. The slope compensation voltage is divided by 10 and is added to the current sense voltage, VI(SENSE). The signal applied to the input of the PWM comparator is a combination of these two voltages. The slope compensation, dVSLOPE/dt, is calculated using the following formula:
dVSLOPE + 0.1 dt 53 mA CS
where R3 is a resistor connected from the OV pin to ground. When the monitored voltage is low and the UV pin is less than 1.45 V, GATE shuts down. The UV pin has fixed 75 mV hysteresis. Both OV and UV conditions are latched until the Soft Start capacitor is discharged. This way, every time a fault condition is detected the controller goes through the power up sequence.
R1 VIN VUV VOV R2 R3
It should be noted that internal capacitance of the IC will cause an error when determining slope compensation capacitance CS. This error is typically small for large values of CS, but increases as CS becomes small and comparable to the internal capacitance. The effect is apparent as a reduction in charging current due to the need to charge the internal capacitance in parallel with CS.Figure 4 shows a typical curve indicating this decrease in available charging current.
60 55 Charging Current (mA) 50 45 40 35 30 25 20 10 100 Compensation Cap (pF) 1000
Figure 5. UV/OV Monitor Divider
To calculate the OV?UV resistor divider : 1. Solve for R3, based on OV hysteresis requirements.
R3 + VOV(HYST) 2.5 V VMAX 12.5 mA
where VOV(HYST) is the desired amount of overvoltage hysteresis, and VMAX is the input voltage at which the supply will shut down. 2. Find the total impedance of the divider.
V R3 RTOT + R1 ) R2 ) R3 + MAX 2.5
3. Determine the value of R2 from the UV threshold conditions.
R2 + 1.45 RTOT * R3 VMIN
where VMIN is the UV voltage at which the supply will shut down. 4. Calculate R1.
R1 + RTOT * R2 * R3
Figure 4. The Slope Compensation Pin Charge Current Reduces When a Small Capacitor Is Used. Undervoltage (UV) and Overvoltage (OV) Monitor
5. The undervoltage hysteresis is given by :
V 0.075 VUV(HYST) + MIN 1.45 VREF Monitor
Two independent comparators monitor OV and UV conditions. A string of three resistors is connected in series between the monitored voltage (usually the input voltage) and ground (see Figure 5). When voltage at the OV pin exceeds 2.5 V, an overvoltage condition is detected and GATE shuts down. An internal 12.5 mA current source turns on and feeds current into the external resistor, R3, creating a hysteresis determined by the value of this resistor (the higher the value, the greater the hysteresis). The hysteresis voltage of the OV monitor is determined by the following formula:
VOV(HYST) + 12.5 mA R3
The 5.0 V reference voltage is internally monitored to ensure that it remains within specifications. The monitor, which outputs a fault, can be tripped by two methods: * If the reference voltage drops below 4.75 V * If VCC falls below the STOP threshold As indicated in the block diagram, any fault causes the output to stop switching and begins the discharge of the Soft Start capacitor CSS.
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CS51021A, CS51022A, CS51023A, CS51024A
Synchronization Oscillator and Duty Cycle Limit
A bi-directional synchronization is provided to synchronize several controllers. When SYNC pins are connected together, the converters will lock to the highest switching frequency. The fastest controller becomes the master, producing a 4.3 V, 200 ns pulse train. Only one, the highest frequency SYNC signal, will appear on the SYNC line.
Sleep
The sleep input is an active high input. The CS51022A/4A is placed in sleep mode when SLEEP is driven high. In sleep mode, the controller and MOSFET are turned off. Connect to GND for normal operation. The sleep mode operates at VCC 15 V.
The switching frequency is set by RT and CT connected to the RTCT pin. CT charges and discharges between 3.0 V and 1.5 V. The maximum duty cycle is set by the ratio of the on time, tON, and the whole period, T = tON + tOFF. Because the timing capacitor's discharge current is trimmed, the maximum duty cycle is well defined. It is determined by the ratio between the timing resistor RT and the timing capacitor CT. Refer to figures 6 and 7 to select appropriate values for RT and CT.
fSW + 1 ;T SW + tCH ) tDIS TSW
2500 1. CT = 47 pF 2. CT = 100 pF 3. CT = 150 pF 4. CT = 220 pF 5. CT = 390 pF 6. CT = 470 pF 7. CT = 560 pF 8. CT = 680 pF
100
7 8
2000 Frequency (kHz)
90 Duty Cycle (%) 80 70
5
6
1
4 3 2 1
1500
2
1000
3 4 5 6 7
60 50 40
500
1. CT = 47 pF 2. CT = 100 pF 3. CT = 150 pF 4. CT = 220 pF 5. CT = 390 pF 6. CT = 470 pF 7. CT = 560 pF 8. CT = 680 pF 35 40 45 50 55
0 5
8
10
15
20
25
30
35
40
45
50
5
10
15
20
25
30 RT (kW)
RT (kW)
Figure 6. Frequency vs. RT for Discrete Capacitor Values
Figure 7. Duty Cycle vs. RT for Discrete Capacitor Values
ORDERING INFORMATION
Device CS51021AED16 CS51021AEDR16 CS51021AEDR16G CS51022ADBG CS51022ADBR2G CS51022AED16 CS51022AEDR16 CS51022AEDR16G CS51023AED16 CS51023AEDR16 CS51023AEDR16G SOIC-16 SOIC-16 (Pb-Free) 2500 Tape & Reel SOIC-16 SOIC-16 (Pb-Free) 2500 Tape & Reel 48 Units / Rail SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 48 Units / Rail Package Shipping 48 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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9
CS51021A, CS51022A, CS51023A, CS51024A
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
PACKAGE THERMAL DATA Parameter RqJC RqJA Typical Typical SOIC-16 28 115 Unit C/W C/W
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CS51021A, CS51022A, CS51023A, CS51024A
TSSOP-16 CASE 948F-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
2X
L/2
16
9
L
PIN 1 IDENT. 1 8
B -U-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.15 (0.006) T U
S
A -V- N K K1 0.25 (0.010) M N F DETAIL E
J1
SECTION N-N J
DIM A B C D F G H J J1 K K1 L M
0.10 (0.004) -T- SEATING
PLANE
D
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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CS51021/D

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